In order to explain the background of the invention, reference will be made to FIGS. 1 to 3:
In FIG. 1, there are two inverters: a first inverter INV1 constituted by a P-channel FET (field effect transistor) 1 and an N-channel FET 2, and a second inverter INV2 constituted by a P-channel FET 3 and an N-channel FET 4. The reference numerals 5 and 6 designate a first and a second input terminal connected to the gates of the N-channel FETs 2 and 4, respectively. The reference numerals 7 and 8 designate a first node and a second node, and the reference numeral 9 designates an output terminal.
Under the above-mentioned arrangement the input terminals 5 and 6 are to be applied by complementary signals, and the P-channel FETs 1 and 3, and the N-channel FETs 2 and 4 are designed such that their conductances g1 to g4 are in the relations of g1=g3 and g2=g4. The four FETs constitute a current-mirror type CMOS amplifier.
Referring to FIGS. 2 and 3, the operation of the circuit shown in FIG. 1 will be described:
In FIG. 2, when the voltages V5 and V6 of the input terminals 5 and 6 are equally Vr, the voltage-current characteristics of the N-channel FET 2 is represented by a curve I2. The voltage-current characteristics of the P-channel FET 1 can be represented by a curve I1 because the drain and the gate thereof are short-circuited. The curves I2 and I1 cross at a point P0, whose potential becomes an output voltage V7 of the first inverter INV1. The conductance of the second inverter INV2 is designed to be the same value as that of the first inverter INV1. The voltage-current characteristics of the P-channel FET 3 can be represented by a curve I3 because the gate thereof is connected to the first node 7, and that of the N-channel FET 4 can be represented by a curve I4. The curves I3 and I4 cross at the point P0, whose potential also becomes an output voltage V8 of the second inverter INV2. In this way the output voltages of the first and the second inverter INV1 and INV2 become equal.
At this stage, when complementary inputs V5a (=Vr+.DELTA.Vr) and V6a (=Vr -.DELTA.Vr) are applied to the input teminals 5 and 6, the curves I2, I3, and I4 change into curves I2a, I3a and I4a, respectively, and the crossing points P0 shift to P1 and P2. As a result, the output voltage V8a of the second inverter INV2 becomes higher than that at the point P0, the higher voltage at the point P2 being designated by VH.
In FIG. 3, when complementary inputs V5b (=Vr -.DELTA.Vr) and V6b (=Vr+.DELTA.Vr) are input to the input terminals 5 and 6, the curves I2, I3 and I4 change into curves I2b, I3b and I4b, and the crossing points P0 shift to P3 and P4. As a result, the output voltage V8b of the second inverter INV2 becomes lower than that at the point P0, the lower voltage at the point P4 being designated by VL.
In this way the input amplitude 2.DELTA.Vr which is a potential difference between the input terminals 5 and 6 is amplified to (VH-VL). That is, when the voltages V5 and V6 of the input terminals 5 and 6 are equal, currents of equal amplitude flow through the first inverter INV1 and the second inverter INV2, as is commonly called a "current mirror". However, it is a waste of electricity when currents of equal amplitude flow through the two inverters INV1 and INV2. This is a great disadvantage with the known devices.